Z80 architecture

Interrupts

The Z80 CPU contains two types on interrupts, maskable, which can be enabled or disabled by the programmer, and nonmaskable, which can't be disabled. For this purpose, the CPU contains two interrupt input pins: INT, for maskable, and NMI, for nonmaskable. To enable interrupts, there is a flip-flop (IFF) that can be either set or reset by the user using specialized instructions (EI, Enable Interrupt, and DI, Disable Interrupt). To account for nonmaskable interrupts, this flip-flop is split into two, IFF1 and IFF2. When a nonmaskable interrupt occurs (pin NMI is asserted), the status of IFF1 is stored in IFF2, and IFF1 is reset to prevent maskable interrupts from interrupting the handler. When a maskable interrupt occurs (pin INT is asserted) and is accepted, interrupts are disabled by clearing both IFF1 and IFF2 @ZilogZ80 pages 17--18.

While nonmaskable interrupts are always handled by restarting the CPU at address 0x0066, maskable interrupts can be handled by one of the three possible modes, set by the programmer. In mode 0, the interrupting device places the next instruction on the data bus, and the CPU executes it. Mode 1 behaves similar to nonmaskable interrupts, by restarting at address 0x0038. Finally, mode 3 implements vectored interrupts, using a 16-bit pointer. The upper eight bits of the pointer are set by the contents of register I, while the lower eight bits are supplied by the interrupting device. As with regular routines, the address of the next instruction (current PC) is stored in the stack before branching to the handler routine, so the execution can be resumed @ZilogZ80 pages 19--20 and 59.

After the handler finishes, the interrupt pin must be reset (In the case that the interrupt was generated by a peripheral device, the device must be notified through the use of an OUT instruction) before re-enabling interrupts, and returning from the routine. A RET instruction (The RET instruction pops the top of the stack and stores it into the PC) may be used to resume execution, but the Z80 ISA offers some alternatives with additional functionality for handling interrupts; the RETN (RETurn from Nonmaskable interrupt) instruction restores the original value of IFF1, while the RETI (RETurn from Interrupt) instruction is recognized by peripherals and automatically notifies them to reset the interrupt pin @ZilogZ80 pages 18 and 59--60.

As a concrete example, the Sinclair ZX Spectrum (Released in 1982 in the UK, it is one of the most popular computers that featured the Z80 family of CPUs.)'s ROM includes maskable and nonmaskable interrupt routines. While the nonmaskable routine forced a system reset, the maskable routine in charge of reading the keyboard, and used a RET instruction instead of RETI, due to the fact that these interrupts were generated by a timer and the INT pin was automatically reset @logan1983complete pages 1--2.

More details in the Master Thesis "Implementing Interrupts, Timers, and Memory-Mapped I/O in CREATOR" By Luis Daniel Casais Mezquida